1. Technical Field
The invention relates generally to integrated circuits, and more specifically, to integrated circuits having high speed complementary metal oxide semiconductor (CMOS) latch circuits.
2. Related Art
Many conventional CMOS latch circuits use cross-coupled inverters having a feedback inverter for latching data within the latch circuit. A data input inverter, usually consisting of a PFET and/or NFET device, clocks data into the cross-coupled inverters. In such a conventional latch, the feedback inverter of the cross-coupled inverters must be smaller than the data input inverter so that the data inverter can overdrive the feedback inverter in order to change the state of the latch. The requirement of different sizes for the inverters, however, makes it difficult to implement the latch in a gate array design where only one device size is available.
In CMOS integrated circuit chips, the power supply voltages are constantly decreasing with each new technology generation. To properly design CMOS latch circuits for use in memory cells, the circuits must be functional at a predetermined low voltage (e.g., 0.6 V) to allow for a margin of uncertainty. Since many conventional CMOS latch circuits require a significant amount of device current to overcome the feedback inverter for changing the state of a latch circuit, this predetermined low voltage may be difficult to achieve.
Some examples of latch circuits that address the problems existing with conventional CMOS latch circuits are found in the following U.S. Patents: U.S. Pat. No. 5,887,004, xe2x80x9cIsolated Scan Paths,xe2x80x9d issued March 1999 to Walther; and U.S. Pat. No. 4,988,896, xe2x80x9cHigh Speed CMOS Latch without Pass-Gates,xe2x80x9d issued January 1991 to Chu.
Walther discloses a method of isolating scan paths, which are used in testing integrated circuits such as latch circuits, to reduce power consumption. Although the power consumption may be reduced through isolating the scan paths, the details of the system path are not disclosed in the Walther reference, and thus, the system will still require a significant amount of device current to change the state of a latch circuit.
Chu discloses a latch circuit that isolates the latch nodes during the clocking cycle so that all of the device current is available to charge the node capacitance. Chu, though, is limited by the clock. That is, the data will not be held or valid in the latch circuit until the clock is released. Hence, when the clock is present, there is a chance for noise and/or invalid data.
Accordingly, a need has developed in the art for a latch circuit that will not only operate at a predetermined low voltage, but will quickly reach a valid state of operation during an active clock signal.
It is thus an advantage of the present invention to provide a latch device that eliminates the above described limitations.
The foregoing and other advantages of the invention are realized by a latch device having a selectable feedback path, wherein the path may be disconnected to allow the latch state to be changed without overdriving a feedback inverter.
Generally, the present invention provides a latch device comprising:
a feedback path;
a retaining device for retaining within said feedback path a logical value to be written out, said logical value being latched during an active clock signal; and
a system isolation device for disconnecting said retaining device from said feedback path during a write operation, and for reconnecting said retaining device in response to the logical value being written out.
In addition, the present invention provides a method for writing and reading a first and second logical value with a latch device having a feedback path comprising the steps of:
a) retaining within said feedback path said first logical value to be written out;
b) disconnecting said feedback path during a write operation;
c) reconnecting said feedback path in response to the first logical value being written out;
d) writing a second logical value into said feedback path of said latch device; and
e) latching said second logical value into said feedback path during an active clock signal.
The present invention also provides an integrated circuit system having a scanable CMOS memory cell, said CMOS memory cell comprising:
a write port receiving a logical value and write signals;
a feedback path;
a retaining device, coupled to said write port, for retaining within said feedback path said logical value, said retaining device latching said logical value during an active clock signal; and
a system isolation device for disconnecting said retaining device from said feedback path during a write operation, and for reconnecting said retaining device in response to the logical value being written out.
The foregoing and other advantages and features of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.